1. Field of the Invention
The invention relates to a testing system, and more particularly to a testing system of a flash memory.
2. Description of the Related Art
In recent years, flash memory has been made to have the characteristics of data non-volatility, low power consumption, a compact size, and a non-mechanical structure. Hence, flash memory has been adapted for various electronic devices, especially portable electronic devices.
In general, a flash memory chip of a flash memory storage device comprises one or more flash memory dies according to various storage capacities. Before the flash memory die is packaged in a flash memory chip, a wafer sorting test is performed, so as to test each memory die of the wafer. After completing the wafer sorting test, good memory dies will be packaged into a chip, e. g. multi-chip package (MCP). If the memory dies of the wafer are not entirely tested before a multi-chip is packaged, a chip may be discarded due to some defective memory dies when a package final test is performed for the chip. Thus, damage is made to good memory dies of the chip and package cost is increased.
Furthermore, the testing apparatuses are complex and expensive for wafer sorting tests. Traditionally, when a wafer sorting test is performed, automatic test equipment (ATE) may write a great quantity of testing data into the die of the wafer to be tested, and then read the written data from the die to be tested. Next, the ATE performs an error checking and correcting (ECC) procedure, to determine whether the die to be tested has defects. Because a great quantity of data is needed for an ECC procedure, a higher level ATE is used to test various memory dies simultaneously. If a lower level ATE is used, it is unable to test various memory dies simultaneously, thereby increasing test time and test cost.
Therefore, a testing apparatus and method thereof for decreasing test costs are desired.